Operating Your Lego Logic Gates
Universal Lego Logic Gates can represent every kind of two-input logic gate, as well as a NOT gate.
In the picture below, the light blue piece (2L lift arm, in Lego lingo) is a pointer that determines which gate is being represented. In the down position, it's an AND gate. Continuing clockwise, in the 9 o'clock position, it's an OR gate. At the 12 o'clock position, it's a NAND gate. Finally, in the 3 o'clock position, it's a NOR gate. The light blue pointer shows which gate is being modeled only when the inputs are both zero (0).
The final two (of six) logic gates can be represented by positioning the dark blue cam (also a 2L lift arm) on the other side of the axle in a straight line opposite the red cam. The two cams would represent 0101 as they rotate. This configuration allows the gate to represent an XOR gate and a XNOR gate.
Below, in the AND gate position, the two input (gray tow balls) are both in the down zero (0) position, with the extension handles forward. The green output arm is also in the down position. For an AND gate, the green output will only be in the up position when yellow input AND blue input are both up.
Below, the yellow input is set to the up one (1) position, with the handle all the way back. The AND green output is still down showing zero (0).
Below, the blue input is set to the up one (1) position, with the handle all the way back. The AND green output is still down showing zero (0).
In the final possible input, both yellow and blue are set to up one (1) with their handles all the way back, the green output is in the up one (1) position. An AND gate only outputs a one (1) when both inputs are one (1).
Reset both arms to zero one at a time and the light blue pointer should be pointing back down indicating an AND gate. To try other logic gates, position the light blue pointer to a different starting position; OR at 9 o'clock, NAND at 12 o'clock, NOR
A NOT gate can be represented by setting the light blue pointer to the NOR position at 3 o'clock and just operating one input lever. The unused lever remains in the zero (0) position. The output will be the negation (opposite) of the input. Alternatively a NOT gate can be represented with a NAND gate if the unused lever remains in the one (1) position. There are two more ways to represent a NOT gate. Can you figure out how and why all four ways work?
